Using Transaction-Based Verification in SystemC

SystemC is a new modeling language based on C++ for hardware and system-level design modeling. This paper examines how a basic transaction-based test bench may be created in the SystemC version 2.0 standard. An example with a pipelined bus interface is presented to illustrate what can be done easily with the latest SystemC version 2.0 distribution [1]. The TestBuilder team is currently creating a TestBuilder-SC library to fill in several missing pieces in SystemC 2.0, in order to support advanced transaction-based verification in a real design development process. While TestBuilder [3] was designed for direct connection to an HDL simulator, TestBuilder-SC acts as a verification layer on top of SystemC. The API in TestBuilder-SC has been proposed to the SystemC’s verification working group to be adopted as a standard. 1