A Systematic Investigation of State-Of-The-Art Systemc Verification

The growing complexity of System-on-a-Chips (SoCs) and rapidly decreasing time-to-market have pushed the design abstraction to the electronic system level in order to increase design productivity. SystemC is a widely used electronic system level modeling language that enables quick prototyping and early verification in the SoC design process. The functional correctness of SystemC designs is often one of the greatest concerns in the SoC design process, since undetected design errors may propagate to low-level implementations or even final silicon products, which are costly to fix. However, SystemC verification is a challenging task due to its complex language features such as object-oriented constructs, hardware-oriented data types and concurrency. A variety of approaches have been proposed for SystemC verification in the past two decades. This work systematically investigates the state-of-the-art SystemC verification approaches by discussing their methodologies, advantages, and limitations, as well as presenting comparison among various approaches