We prove the correctness of compilation of relaxed memory accesses and release-acquire fences from the "promising" semantics of [Kang et al. POPL\u2717] to the ARMv8 POP machine of [Flur et al. POPL\u2716]. The proof is highly non-trivial because both the ARMv8 POP and the promising semantics provide some extremely weak consistency guarantees for normal memory accesses; however, they do so in rather different ways. Our proof of compilation correctness to ARMv8 POP strengthens the results of the Kang et al., who only proved the correctness of compilation to x86-TSO and Power, which are much simpler in comparison to ARMv8 POP
Robustness of a concurrent program ensures that its behaviors on a weak concurrency model are indis...
International audienceComputing relies on architecture specifications to decouple hardware and softw...
International audienceThere is a joke where a physicist and a mathematician are asked to herd cats. ...
Weakestmo is a recently proposed memory consistency model that uses event structures to resolve the ...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and ARMv8. Over tim...
Shared memory concurrency is the pervasive programming model for multicore architectures such as x8...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and AR...
Virtual memory is an essential mechanism for enforcing security boundaries, but its relaxed-memory c...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and ARMv8. Over tim...
Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consisten...
Hardware weak memory models, such as TSO and ARM, are used to increase the performance of concurrent...
AbstractComputing relies on architecture specifications to decouple hardware and software developmen...
The integration of transactions into hardware relaxed memory architectures is a topic of current res...
Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance...
Previous work on the semantics of relaxed shared-memory concurrency has only considered the case in ...
Robustness of a concurrent program ensures that its behaviors on a weak concurrency model are indis...
International audienceComputing relies on architecture specifications to decouple hardware and softw...
International audienceThere is a joke where a physicist and a mathematician are asked to herd cats. ...
Weakestmo is a recently proposed memory consistency model that uses event structures to resolve the ...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and ARMv8. Over tim...
Shared memory concurrency is the pervasive programming model for multicore architectures such as x8...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and AR...
Virtual memory is an essential mechanism for enforcing security boundaries, but its relaxed-memory c...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and ARMv8. Over tim...
Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consisten...
Hardware weak memory models, such as TSO and ARM, are used to increase the performance of concurrent...
AbstractComputing relies on architecture specifications to decouple hardware and software developmen...
The integration of transactions into hardware relaxed memory architectures is a topic of current res...
Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance...
Previous work on the semantics of relaxed shared-memory concurrency has only considered the case in ...
Robustness of a concurrent program ensures that its behaviors on a weak concurrency model are indis...
International audienceComputing relies on architecture specifications to decouple hardware and softw...
International audienceThere is a joke where a physicist and a mathematician are asked to herd cats. ...