Robustness of a concurrent program ensures that its behaviors on a weak concurrency model are indistinguishable from those on a stronger model. Enforcing robustness is particularly useful when porting or migrating applications between architectures. Existing tools mostly focus on ensuring sequential consistency (SC) robustness which is a stronger condition and may result in unnecessary fences. To address this gap, we analyze and enforce robustness between weak memory models, more specifically for two mainstream architectures: x86 and ARM (versions 7 and 8). We identify robustness conditions and develop analysis techniques that facilitate porting an application between these architectures. To the best of our knowledge, this is th...
When a program is compiled and run on a modern architecture, different optimizations may be applied ...
Weak-memory models are standard formal specifications of concurrency across hardware, programming la...
Weak memory models formalize the inconsistent behaviors that one can expect to observe in multithrea...
Robustness of a concurrent program ensures that its behaviors on a weak concurrency model are indist...
Developing correct and performant concurrent systems is a major challenge. When programming an appli...
Sequential Consistency (SC) is the memory model traditionally applied by programmers and verificatio...
International audienceConcurrent programs running on weak memory models exhibit re-laxed behaviours,...
Weak consistency is a memory model that is frequently considered for shared memory systems. Its most...
Robustness is a correctness notion for concurrent programs running under relaxed consistency models....
Weak memory models are used to increase the performance of concurrent programs by allowing program i...
For performance reasons, modern multiprocessors implement relaxed memory consistency models that adm...
Hardware weak memory models, such as TSO and ARM, are used to increase the performance of concurrent...
Writing concurrent programs with shared memory is often not trivial. Correctly synchronising the thr...
Memory models of shared memory concurrent programs define the values a read of a shared memory locat...
Weak memory models formalize the unexpected behavior that one can expect to observe in multi-threade...
When a program is compiled and run on a modern architecture, different optimizations may be applied ...
Weak-memory models are standard formal specifications of concurrency across hardware, programming la...
Weak memory models formalize the inconsistent behaviors that one can expect to observe in multithrea...
Robustness of a concurrent program ensures that its behaviors on a weak concurrency model are indist...
Developing correct and performant concurrent systems is a major challenge. When programming an appli...
Sequential Consistency (SC) is the memory model traditionally applied by programmers and verificatio...
International audienceConcurrent programs running on weak memory models exhibit re-laxed behaviours,...
Weak consistency is a memory model that is frequently considered for shared memory systems. Its most...
Robustness is a correctness notion for concurrent programs running under relaxed consistency models....
Weak memory models are used to increase the performance of concurrent programs by allowing program i...
For performance reasons, modern multiprocessors implement relaxed memory consistency models that adm...
Hardware weak memory models, such as TSO and ARM, are used to increase the performance of concurrent...
Writing concurrent programs with shared memory is often not trivial. Correctly synchronising the thr...
Memory models of shared memory concurrent programs define the values a read of a shared memory locat...
Weak memory models formalize the unexpected behavior that one can expect to observe in multi-threade...
When a program is compiled and run on a modern architecture, different optimizations may be applied ...
Weak-memory models are standard formal specifications of concurrency across hardware, programming la...
Weak memory models formalize the inconsistent behaviors that one can expect to observe in multithrea...