Statistical modeling and simulation of variability and reliability of CMOS technology

The introduction of High-κ Metal Gate transistors led to higher integration density, low leakage current, and faster switching speed. However, this transition in technology roadmap brought about new failure mechanisms such as Positive Bias Temperature Instability and Stress Induced Leakage Current. In addition, the relentless downscaling of devices to keep up with Moore\u27s law has significantly increased the time-zero variability caused by Random Dopant Fluctuation, Mean Gate Length Deviation, and Line Edge Roughness. Because of their possible correlation with time dependent aging effects, the quantification of reliability has become more complex than ever. To that effect, we propose a framework to analyze the stochastic nature of different reliability issues and their impact at the circuit level. Our Bias Temperature Instability model for trap generation in NMOS transistors captures both time dependent threshold voltage degradation as well as dielectric breakdown of oxide layers. In addition, we incorporated our model into a Technology Computer Aided Design device simulator in order to capture the correlation between time-zero and time-dependent variability. We observed that the correlation is small, yet significant in the device lifetime prediction. In order to accurately estimate the total guard band necessary for a variation aware Integrated Circuit design, process induced time-zero variation and different aging effects need to be considered simultaneously. In addition, the FinFET architecture can cause additional degradation of the transistors. The field-crowding and 2D-hydrogen diffusion at the fin corners can make the reliability assessment more complicated compared to the planar counterpart. We also proposed a unified model and simulation framework for reliability analysis in tri-gate FinFET devices. The proposed models and simulation framework can be equally applicable to sub-10nm technology nodes