Synthesis aspects in the design of efficient processor arrays from affine recurrence equations

Efficient implementation of problems on processor arrays requires dedicated compiling techniques. This paper proposes synthesis techniques in the design of processor array architectures from system of affine recurrence equations. They implement the spacetime mapping which determine the scheduling of the calculations and the allocation of these calculations to a surface of processors. The paper emphazises the two-steps space mapping which is composed of a classical linear allocation followed by the application of two specific partitioning techniques. These techniques reduce the number of processors and therefore result in more efficient parallel solutions. The paper is illustrated with the Cholesky factorization