Graduation date: 1995In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed\ud and developed. Using multi-coordinate systems (MCS), a unified theory for mapping\ud algorithms from their original algorithmic specifications onto multi-rate arrays is\ud developed.\ud A multi-rate array is a grid of processors in which each interconnection may have its\ud own clock rate; operations with different complexities run at their own clock rate, thus\ud increasing the throughput and efficiency.\ud A class of algorithms named directional affine recurrence equations (DARE) is\ud defined. The dependence space of a DARE can be decomposed into uniform and non-uniform\ud subspaces. When projected along the non-uniform subspa...
With the continuing growth of VLSI technology, special-purpose parallel processors have become a pro...
AbstractMost work on the problem of synthesizing a systolic array from a system of recurrence equati...
Two approaches to architecture-independent parallel computation are investigated: a constructive fun...
Graduation date: 1990Advances in VLSI array processing have led to many new\ud parallel structures f...
Efficient implementation of problems on processor arrays requires dedicated compiling techniques. Th...
Graduation date: 1992Many systematic methods exist for mapping algorithms to processor arrays. The\u...
AbstractThis paper describes a new method of automatic generation of concurrent programs which const...
This paper adresses the problem of efficient mappings of nested loops, and more generally of system...
Journal ArticleWe present a technique for mapping recurrence equations to systolic arrays. While thi...
PhD ThesisSynthesis techniques for regular arrays provide a disciplined and well-founded approach to...
Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually s...
Most existing methods of mapping algorithms into processor arrays are restricted to the case where n...
In this paper, we describe a methodology and a single notation for the specification and verificati...
A high speed parallel array data processing architecture fashioned under a computational envelope ap...
Abstract — This paper introduces methods for extending the classical systolic synthesis methodology ...
With the continuing growth of VLSI technology, special-purpose parallel processors have become a pro...
AbstractMost work on the problem of synthesizing a systolic array from a system of recurrence equati...
Two approaches to architecture-independent parallel computation are investigated: a constructive fun...
Graduation date: 1990Advances in VLSI array processing have led to many new\ud parallel structures f...
Efficient implementation of problems on processor arrays requires dedicated compiling techniques. Th...
Graduation date: 1992Many systematic methods exist for mapping algorithms to processor arrays. The\u...
AbstractThis paper describes a new method of automatic generation of concurrent programs which const...
This paper adresses the problem of efficient mappings of nested loops, and more generally of system...
Journal ArticleWe present a technique for mapping recurrence equations to systolic arrays. While thi...
PhD ThesisSynthesis techniques for regular arrays provide a disciplined and well-founded approach to...
Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually s...
Most existing methods of mapping algorithms into processor arrays are restricted to the case where n...
In this paper, we describe a methodology and a single notation for the specification and verificati...
A high speed parallel array data processing architecture fashioned under a computational envelope ap...
Abstract — This paper introduces methods for extending the classical systolic synthesis methodology ...
With the continuing growth of VLSI technology, special-purpose parallel processors have become a pro...
AbstractMost work on the problem of synthesizing a systolic array from a system of recurrence equati...
Two approaches to architecture-independent parallel computation are investigated: a constructive fun...