Frequency shift keying demodulators for low-power FPGA applications

Master of ScienceDepartment of Electrical and Computer EngineeringDwight D. DayLow-power systems implemented on Field Programmable Gate Arrays (FPGA) have become more practical with advancements leading to decreases in FPGA power consumption, physical size, and cost. In systems that may need to operate for an extended time independent of a central power source, low-power FPGA’s are now a reasonable option. Combined with research into energy harvesting solutions, a FPGA-based system could operate independently indefinitely and be cost effective. Four simple demodulator designs were implemented on a FPGA to test and compare the performance and power consumption of each. The demodulators were a Counter that tracked the length of the input signal period, a One-Shot that counted the input edges over time, a Phase-Frequency Detector (PFD), and a PFD with preprocessing on the input signal to mitigate distortion introduces by the 1-bit subsampling. The designs demodulated a binary frequency shift keying (BFSK) signal using 10.69MHz and 10.71MHz as the input frequencies and a 1kHz data rate. The signal was 1-bit subsampled at 75kHz to provide the demodulators with a signal containing 15kHz and 35kHz. The design size, power consumption, and error performance of each demodulator were compared. At the frequencies and data rate used, the Counter and One-Shot are the most energy efficient by a significant margin over the PFDs. The error performance was nearly equal for all four. As the BFSK baseband frequencies and especially the data rate are increased, the PFD options are expected to be the better options as the Counter and One-Shot may not react quickly enough