We propose a new machine architecture for high performance execution of late binding object oriented languages. The two principal mechanisms for attaining this goal are a fast context allocation/access scheme and an instruction translation lookaside buffer. New ideas in this paper include the concept and implementation of abstract instructions, using floating point addresses to solve the small object problem, and a novel context allocation/access mechanism
The vast divide between the speed of CPU and RAM means that effective use of CPU caches is often a p...
Although large-scale shared-memory multiprocessors are believed to be easier to program than disjoin...
Due to the growing mismatch between processor performance and memory latency, many dynamic mechanism...
We propose a new machine architecture for high performance execution of late binding object oriente...
We propose a new machine architecture for high performance execution of late binding object oriented...
In the past, many persistent object-oriented architecture designs have been based on traditional pro...
A homogeneous machine architecture, consisting of a regular interconnection of many identical elemen...
Based on an empirical study of more than 10,000 lines of program text written in a GOTO-less languag...
Object-oriented programming languages where classes are top-level, i.e. not first-class citizens, ar...
As the gap between memory and processor performance continues to grow, more and more programs will ...
A homogeneous machine architecture, consisting of a regular interconnection of many identical eleme...
Micro-architecture designs and methods are provided. A computer processing architecture may include ...
. In this paper we describe the implementation of a multithreaded trace-driven address translation s...
(INSTRUCTION LINE ASSOCIATIVE REGISTERS) Due to the growing mismatch between processor performance a...
Journal ArticleModern superscalar processors use wide instruction issue widths and out-of-order exe...
The vast divide between the speed of CPU and RAM means that effective use of CPU caches is often a p...
Although large-scale shared-memory multiprocessors are believed to be easier to program than disjoin...
Due to the growing mismatch between processor performance and memory latency, many dynamic mechanism...
We propose a new machine architecture for high performance execution of late binding object oriente...
We propose a new machine architecture for high performance execution of late binding object oriented...
In the past, many persistent object-oriented architecture designs have been based on traditional pro...
A homogeneous machine architecture, consisting of a regular interconnection of many identical elemen...
Based on an empirical study of more than 10,000 lines of program text written in a GOTO-less languag...
Object-oriented programming languages where classes are top-level, i.e. not first-class citizens, ar...
As the gap between memory and processor performance continues to grow, more and more programs will ...
A homogeneous machine architecture, consisting of a regular interconnection of many identical eleme...
Micro-architecture designs and methods are provided. A computer processing architecture may include ...
. In this paper we describe the implementation of a multithreaded trace-driven address translation s...
(INSTRUCTION LINE ASSOCIATIVE REGISTERS) Due to the growing mismatch between processor performance a...
Journal ArticleModern superscalar processors use wide instruction issue widths and out-of-order exe...
The vast divide between the speed of CPU and RAM means that effective use of CPU caches is often a p...
Although large-scale shared-memory multiprocessors are believed to be easier to program than disjoin...
Due to the growing mismatch between processor performance and memory latency, many dynamic mechanism...