Improving GPGPU NoC Performance with Memory Controller Placement Awareness

Graduation date: 2017General-purpose Graphics Processing Units (GPGPUs) have become a critical component in high-performance computing (HPC) systems in executing modern computational workloads. The high thread level parallelism (TLP) and programmable shader cores allow thousands of threads to execute in Parallel. The fast-scaling of GPGPUs have increased the demand for performance optimizations on Network-On-Chip (NoC) designs. Previous works have exploited NoC designs in the Chip Multiprocessor (CMP) environments but not much in GPGPU systems. Unlike CMPs, traffic is highly asymmetric in GPGPUs because of the many cores but very few memory controllers (MCs). The asymmetric traffic impacts the resource utilization and performance of NoCs. This work aims at analyzing the maximum channel load associated with different MC placements and VC partitioning in interconnection networks of GPGPUs. We also utilize the recently introduced concept of VC monopolization and propose new ways to reduce link contention and improve performance. Evaluation results from cycle-accurate simulation and representative workloads show that the proposed scheme increases application performance (IPC) by 14%, on average, and reduces interconnection network packet latency by 21%