Efficient transmission of triangle meshes to graphics processors

[[abstract]]The performance of VLSI graphics processors is rising rapidly with the incorporation of specialized 3D geometry processing hardware into the graphics accelerator. Due to memory and bus bandwidth limitations, host systems often cannot deliver geometric data to graphics processors fast enough to saturate their processing capability. This paper proposes a compression scheme designed to alleviate the bandwidth bottleneck by transmitting triangle meshes to the graphics engine as an instruction stream. Controlling a vertex cache within the graphics subsystem allows redundant vertex transmissions and thus transformations to be virtually eliminated. The non-vertex bandwidth overhead is approximately 2-4 bits/triangle, which is less than half the overhead of competing techniques[[fileno]]2030236030082[[department]]資訊工程學