A systolic architecture for computing inverses in finite fields GF (2m)

[[abstract]]© 1991 Institute of Electrical and Electronics Engineers - In this paper, a new serial-in serial-out systolic array is presented for fast inversion in finite fields GF(2m) with the standard basis representation. The architecture is highly regular, modular, nearest neighbor connected, and thus well suited to VLSI implementation. It has a latency of 7m-3 clock cycles and a throughput rate of one result per 2m-1 clock cycles. This speed performance is much better than those in the related systems described previously. Moreover, its logic circuit design is independent of the primitive polynomial used to generate the field. As a consequence, the proposed system is useful for a wide range of applications[[department]]電機工程學