High-Speed Systolic Architectures for Finite Field Inversion and Division ∗

Based on a new reformulation of the extended Euclidean al-gorithm, systolic architectures suitable for VLSI implemen-tations are proposed for finite field inversion and division in this paper. The architectures proposed in this paper can achieve O(m2) area-time complexity, O(m) latency, and crit-ical path delays of two logic gates. These architectures show improved performances when compared with previously pro-posed architectures. Categories and Subject Descriptors B.2.4 [ARITHMETIC AND LOGIC STRUCTURES]