[[abstract]]Directory hints help a node in a NOW-based shared memory multiprocessor to keep track where valid copies of a memory block may reside. With this information the node can fetch the block directly from those nodes on a read miss. In this way the number of network transactions to serve the miss may be reduced and the expensive directory lookup operation may be removed from the critical path. In this paper we discuss the issues involved in implementing the directory hint scheme on a NOW-based shared memory multiprocessor and examine one such implementation, which employs a small and fast cache to store the hints. Our simulation results show that the directory hint scheme can effectively reduce the read stall time. Also its performan...
Recent research shows that the occupancy of the coherence controllers is a major performance bottlen...
This paper presents the design and evaluation of the M-cache, a small, fast and intelligent memory f...
The performance gap between processor and memory continues to remain a major performance bottleneck ...
[[abstract]]Directory hints (DHs) help a node in a cache coherent non-uniform memory (CC-NUMA) share...
[[abstract]]Directory hints (DHs) help a node in a cache coherent non-uniform memory (CC-NUMA) share...
This dissertation focuses on caching in distributed file systems, where the performance is constrain...
As computing power has increased over the past few decades, science and engineering have found more ...
We present a very low-overhead decentralized algorithm for cooperative caching that provides perform...
Nowadays, most computer manufacturers offer chip multiprocessors (CMPs) due to the always increasing...
[[abstract]]© 2006 Springer Verlag-Using caching to enhance performance has been widely used in the ...
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue...
textThis dissertation explores techniques for reducing the costs of inter-processor communication i...
Design complexity and limited power budget are causing the number of cores on the same chip to grow ...
Distributed hash tables are increasingly being proposed as the core substrate for content delivery a...
Presented to the 12th Annual Symposium on Graduate Research and Scholarly Projects (GRASP) held at ...
Recent research shows that the occupancy of the coherence controllers is a major performance bottlen...
This paper presents the design and evaluation of the M-cache, a small, fast and intelligent memory f...
The performance gap between processor and memory continues to remain a major performance bottleneck ...
[[abstract]]Directory hints (DHs) help a node in a cache coherent non-uniform memory (CC-NUMA) share...
[[abstract]]Directory hints (DHs) help a node in a cache coherent non-uniform memory (CC-NUMA) share...
This dissertation focuses on caching in distributed file systems, where the performance is constrain...
As computing power has increased over the past few decades, science and engineering have found more ...
We present a very low-overhead decentralized algorithm for cooperative caching that provides perform...
Nowadays, most computer manufacturers offer chip multiprocessors (CMPs) due to the always increasing...
[[abstract]]© 2006 Springer Verlag-Using caching to enhance performance has been widely used in the ...
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue...
textThis dissertation explores techniques for reducing the costs of inter-processor communication i...
Design complexity and limited power budget are causing the number of cores on the same chip to grow ...
Distributed hash tables are increasingly being proposed as the core substrate for content delivery a...
Presented to the 12th Annual Symposium on Graduate Research and Scholarly Projects (GRASP) held at ...
Recent research shows that the occupancy of the coherence controllers is a major performance bottlen...
This paper presents the design and evaluation of the M-cache, a small, fast and intelligent memory f...
The performance gap between processor and memory continues to remain a major performance bottleneck ...