Nowadays, most computer manufacturers offer chip multiprocessors (CMPs) due to the always increasing chip density. These CMPs have a broad range of characteristics, but all of them support the shared memory programming model. As a result, every CMP implements a coherence protocol to keep local caches coherent. Coherence protocols consume an important fraction of power to determine which coherence action to perform. Specifically, on CMPs with write-through local caches, a shared cache and a directory-based coherence protocol implemented as a duplicate of local caches tags, we have observed that energy is wasted in the directory due to two main reasons. Firstly, an important fraction of directory lookups are useless, because the target block ...
Abstract. If current trends continue, today’s small-scale general-purpose CMPs will soon be replaced...
As the number of cores increases in both incoming and future shared-memory chip--multiprocessor (CMP...
Abstract The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (...
Coherence protocols consume an important fraction of power to determine which coherence action shoul...
Abstract—Coherence protocols consume an important frac-tion of power to determine which coherence ac...
A key challenge in architecting a multicore processor is efficiently maintaining cache coherence. Di...
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue...
Future CMP designs that will integrate tens of processor cores on-chip will be constrained by area a...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
Abstract — Although directory-based cache coher-ence protocols are the best choice when designing la...
Abstract—This paper evaluates several techniques to save leakage in CMP L2 caches by selectively swi...
To support legacy software, large CMPs often provide cache coherence via an on-chip directory rathe...
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching of...
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industr...
Todays systems are designed with Multi Core Architecture. The idea behind this is to achieve high sy...
Abstract. If current trends continue, today’s small-scale general-purpose CMPs will soon be replaced...
As the number of cores increases in both incoming and future shared-memory chip--multiprocessor (CMP...
Abstract The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (...
Coherence protocols consume an important fraction of power to determine which coherence action shoul...
Abstract—Coherence protocols consume an important frac-tion of power to determine which coherence ac...
A key challenge in architecting a multicore processor is efficiently maintaining cache coherence. Di...
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue...
Future CMP designs that will integrate tens of processor cores on-chip will be constrained by area a...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
Abstract — Although directory-based cache coher-ence protocols are the best choice when designing la...
Abstract—This paper evaluates several techniques to save leakage in CMP L2 caches by selectively swi...
To support legacy software, large CMPs often provide cache coherence via an on-chip directory rathe...
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching of...
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industr...
Todays systems are designed with Multi Core Architecture. The idea behind this is to achieve high sy...
Abstract. If current trends continue, today’s small-scale general-purpose CMPs will soon be replaced...
As the number of cores increases in both incoming and future shared-memory chip--multiprocessor (CMP...
Abstract The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (...