[[abstract]]Multimedia, image processing and other signal processing applications often involve data stored in large arrays. Due to chip area limitation, arrays are typically assigned to off-chip memories, such as DRAM. This being the case, we try to optimize off-chip memory accesses to improve performance. We take the characteristics of the current mainstream SDRAM memory into account. We propose an algorithm to allocate arrays to different banks to increase the probability of utilizing SDRAM's multi-bank characteristic. Experimental results show significant improvement over traditional approaches[[fileno]]2030207030051[[department]]資訊工程學
The architecture of the present video processing units in consumer systems is usually based on vario...
Abstract—This paper presents a compiler strategy to optimize data accesses in regular array-intensiv...
Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and applicati...
A modern real-time embedded system must support multiple concurrently running applications. To reduc...
Transactional workloads have storage request streams consisting of many small, independent, random r...
MPSoCs are gaining popularity because of its potential to solve computationally expensive applicatio...
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two re...
The bandwidth mismatch between processor and main memory is one major limiting problem. Although str...
Modern DRAMs have multiple banks to serve multiple mem-ory requests in parallel. However, when two r...
We present a novel and systematic approach for the design of shared memory architectures in the case...
PosterDRAM vendors have traditionally optimized for low cost and high performance, often making desi...
International audienceIn today's embedded systems, memory hierarchy is rapidly becoming a major fact...
The literature has witnessed much work aimed at improving the efficiency of mernory systems. The mot...
As the performance gap between microprocessors and memory continues to increase, main memory accesse...
Submitted on behalf of EDAA (http://www.edaa.com/)International audienceThe aggressive application o...
The architecture of the present video processing units in consumer systems is usually based on vario...
Abstract—This paper presents a compiler strategy to optimize data accesses in regular array-intensiv...
Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and applicati...
A modern real-time embedded system must support multiple concurrently running applications. To reduc...
Transactional workloads have storage request streams consisting of many small, independent, random r...
MPSoCs are gaining popularity because of its potential to solve computationally expensive applicatio...
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two re...
The bandwidth mismatch between processor and main memory is one major limiting problem. Although str...
Modern DRAMs have multiple banks to serve multiple mem-ory requests in parallel. However, when two r...
We present a novel and systematic approach for the design of shared memory architectures in the case...
PosterDRAM vendors have traditionally optimized for low cost and high performance, often making desi...
International audienceIn today's embedded systems, memory hierarchy is rapidly becoming a major fact...
The literature has witnessed much work aimed at improving the efficiency of mernory systems. The mot...
As the performance gap between microprocessors and memory continues to increase, main memory accesse...
Submitted on behalf of EDAA (http://www.edaa.com/)International audienceThe aggressive application o...
The architecture of the present video processing units in consumer systems is usually based on vario...
Abstract—This paper presents a compiler strategy to optimize data accesses in regular array-intensiv...
Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and applicati...