We present a novel and systematic approach for the design of shared memory architectures in the case of application-specific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based on an integer linear programming model. It permits one to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application. The effectiveness of this approach is illustrated by a packet routing switch example
The integration of an increasing amount of on-chip hardware in Chip-Multiprocessors (CMPs) poses a c...
Memory and communication architectures have a significant impact on the cost, performance, and time-...
Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and applicati...
ISBN 2-913329-89-6The last years saw a great evolution in the manufacture technology of the integrat...
This thesis investigates the problems of allocating the data and code address spaces of a concurren...
Optimization of interconnects among processors and memories becomes important as multiple processors...
Memory and communication architectures have a significant impact on the cost, performance, and t...
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because o...
International audienceNext generation FPGA circuits will allow the integration of dozens of hard and...
Memory and communication architectures have a significant impact on the cost, performance, and timet...
VLSI'01 post conference bookMemory represents a major bottleneck in embedded systems. For multimedia...
One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory ...
Memory represents a major bottleneck in embedded systems. Multimedia applications bulky in data in t...
International audienceThe majority of applications, ranging from the low complexity to very multifac...
This paper is devoted to the design of communication and memory architectures of massively parallel ...
The integration of an increasing amount of on-chip hardware in Chip-Multiprocessors (CMPs) poses a c...
Memory and communication architectures have a significant impact on the cost, performance, and time-...
Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and applicati...
ISBN 2-913329-89-6The last years saw a great evolution in the manufacture technology of the integrat...
This thesis investigates the problems of allocating the data and code address spaces of a concurren...
Optimization of interconnects among processors and memories becomes important as multiple processors...
Memory and communication architectures have a significant impact on the cost, performance, and t...
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because o...
International audienceNext generation FPGA circuits will allow the integration of dozens of hard and...
Memory and communication architectures have a significant impact on the cost, performance, and timet...
VLSI'01 post conference bookMemory represents a major bottleneck in embedded systems. For multimedia...
One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory ...
Memory represents a major bottleneck in embedded systems. Multimedia applications bulky in data in t...
International audienceThe majority of applications, ranging from the low complexity to very multifac...
This paper is devoted to the design of communication and memory architectures of massively parallel ...
The integration of an increasing amount of on-chip hardware in Chip-Multiprocessors (CMPs) poses a c...
Memory and communication architectures have a significant impact on the cost, performance, and time-...
Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and applicati...