Effect of resolved branches on the performance of delayed branching

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references.Issued also on microfiche from Lange Micrographics.The impact of resolved branch instructions on the performance of the delayed branching scheme is studied for a two-instruction-issue superscalar pipelined RISC processor. Two processor models are created in Verilog HDL, one with resolved branches using delayed branching scheme (Model 1) and the other without delayed branching for resolved branches (Model 2). A comparison of these two models yields the performance implications of resolved branch instructions. A brief introduction to the performance effects of branches is followed by a description of the implementation details. Benchmark programs are run to obtain results regarding the throughputs offered by the two models. Model 1 is found to outperform Model 2 for all benchmarks. It is concluded that resolved branches do play a significant role in the performance of the delayed branching scheme. It is often possible to fill up the delay slots occurring due to resolved branch instructions with some useful instructions. This recommends that resolved branches be considered for all performance issues related to delayed branching