Branch prediction for a RISC-V processor core

A processor’s performance is measured using metrics of speed and accuracy. These are, however, not independent of one another. The more accurately a processor does what it is supposed to, the less time is spent correcting mistakes, in turn increasing its speed. An inevitable source of inaccuracy involves branch instructions. Not knowing whether a branch is going to be executed or not before it needs to be executed means that a considerable amount of clock cycles are wasted doing incorrect things. This can be avoided using a technique called Branch Prediction. This thesis focuses on understanding the ®CV32E40X processor core, and exploring how the branch prediction will affect the performance, area, and power consumption for the processor core. The Backwards Branch Predictor was implemented based on the models made for the course TFE4580: Electronic Systems Design and Innovation, Specialization Project. The thesis builds upon the work done in the previous course. This thesis provides corrected results for the modeling done for the Specialization Project, as these results were central for the scope of this thesis. The thesis also presents Further Work that can be done to further investigate and potentially improve the performance of the ®CV32E40X processor core. It was found that implementing a backwards predictor allowed for decreasing the number of cycles consumed per benchmark test by about 0.9% in the worst case, and 4.5% for the best case