FORCING SOME ARCHITECTURAL CEILINGS OF THE ACTUAL PROCESSOR PARADIGM

Abstract: In our previously published research we discovered some very difficult to predict branches, called unbiased branches that have a “random ” dynamic behavior. We developed some state of the art branch predictors to successfully predict them. Even these powerful predictors obtained very modest average prediction accuracies on the unbiased branches whereas their global average prediction accuracies are high. The unbiased branches still restrict the ceiling of dynamic branch prediction and therefore accurately predicting them remains an open problem. Since the overall performance of modern superscalar processors is seriously affected by misprediction recovery, especially these difficult branches represent a source of important performance penalties. Our statistics show that about 28.68 % of branches are dependent on critical Load instructions. Moreover, 5.61 % of branches are unbiased and depend on critical Loads, too. These dependences involve high-penalty mispredictions becoming serious performance obstacles and causing significant performance degradation. The negative impact of (unbiased) branches over global performance should be seriously attenuated by anticipating the results of long-latency instructions, including critical Loads. On the other hand, hiding instructions ’ lon