Dynamic Timing Enhanced Computing for Microprocessor and Deep Learning Accelerators

Modern microprocessors such as CPU, GPU, and the recent deep learning accelerators exhibit significant runtime timing variation, i.e. dynamic timing slack due to the diverse instructions and programs being executed inside the processor cores. Many studies show that only in a small fraction of the system execution, e.g. 13% of the time, the processors fully occupy its dedicated clock cycle. This brings a new opportunity to enhance the processors and accelerators\u27 performance by exploiting the dynamic timing slack based on the instructions being executed inside the programs. This chapter presents the recent developments on the “dynamic timing enhanced computing scheme” where excessive runtime timing margin is utilized for boosting the computing performance on both microprocessors and deep learning accelerators. Simulation and test chip measurement results are presented to elaborate the benefits of the dynamic timing enhanced computing scheme in terms of performance and energy saving on modern processors. Both hardware design and software techniques using compiler optimization are presented as a holistic solution