TIME-CONSTRAINED DESIGN OF PIPELINED CONTROL-INTENSIVE SYSTEMS

Although there are widely known solutions for dataflow-dominated resource constrained high-level synthesis (HLS) problems, optimization of hardware resources under time-constraints in control-intensive systems is still a challenge. This paper examines the case when functional pipelining is used to increase the throughput of the system. The traditional concept of mutually exclusive conditional branches must be dropped and new methods are needed to exploit the resource sharing possibilities of conditional branches. We developed new methodologies able to exploit the resource sharing possibilities under these circumstances and extended the two schedulers and the allocation module of the HLS tool PIPE to handle arbitrarily nested conditional structures and demonstrated the improved resource utilization on control-intensive benchmarks