Gate-level design methodology for side-channel resistant logic styles using TFETs

The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an effective solution to secure applications with power constraints. This letter deals with the optimized design of differential power analysis (DPA)-resilient hiding-based techniques, using tunnel field-effect transistors (TFETs). Specifically, proposed TFET implementations of dual-precharge-logic primitives optimizing their computation tree in three different ways are applied to the design of the PRIDE 4-bit substitution box, the most vulnerable block of the PRIDE lightweight cipher. The performance of simulation-based DPA attacks on the proposals has shown spectacular results in security gain (34 out of 48 attacks fail for optimized computation trees in TFET technology) and power reduction ( ×25 ), compared to their CMOS-based counterparts in 65 nm, which is a significant advance in the development of secure circuits with TFETs.This work was partially funded by the Spanish Government with support from FEDER under Projects TEC2017-87052-P and PID2020-116664RB-I00, by Programa Operativo FEDER 2014-2020 and Consejeria de Economia, Conocimiento, Empresas y Universidad de la Junta de Andalucia (Projects US1380876 and US-1380823) and by the SPIRS and SCARE Projects with Grant Agreement No. 952622 and No. 804476, respectively, under the European Union’s Horizon 2020 research and innovation programmePeer reviewe