The EPYC processors are the latest generation of processors from AMD Inc. While they not yet show large adaptation on the top-500 list their performance might change this in the future. The processors are based on x86-64 architecture and provide vector units for a range of different data types, the most relevant being 64-bits floating point. Vector units are 256 bits wide and can operate on four double precision (64-bits) numbers at a time. The processors feature a high number of memory controllers, 8 in the EPYC 7601 model (see [6] for details) that was used for evaluation in the writing of this guide. They also provide 128 PCIe version 3.0 lanes. This guide provides information about how to use the AMD EPYC processors in an HPC environmen...
Automated code generation and performance tuning tech-niques for concurrent architectures such as GP...
The Work Package 7 ‘Application Enabling and Support’ provides applications enabling services for HP...
In the ever-growing complexity of computer architectures, code optimisation has become the main rout...
This course covers techniques for improving the performance of parallel applications by optimising o...
This Best Practice Guide (BPG) extends the previously developed series of BPGs by providing an updat...
This Best Practice Guide provides information about Intel's Haswell/Broadwell architecture in order ...
The ARM processor is heavily used in mobile phones and has the reputation of being very energy effic...
This Best Practice Guide provides information about Intel’s Many Integrated Core (MIC) architecture ...
[[abstract]]A number recently released numerical libraries including automatically tuned linear alge...
This best practice guide provides information about Intel's MIC architecture and programming models ...
Hardware accelerators are special types of elements designed for boosting the performance of certain...
In this paper we discuss new Intel instruction extensions - Intel Advance Vector Extensions 2 (AVX2)...
Energy per Instruction (EPI) is a measure of the amount of energy expended by a microprocessor for e...
This book presents the background of the ARM architecture and outlines the features of the processor...
The authors describe an intelligent EPROM silicon compiler. The compiler accepts high-level specific...
Automated code generation and performance tuning tech-niques for concurrent architectures such as GP...
The Work Package 7 ‘Application Enabling and Support’ provides applications enabling services for HP...
In the ever-growing complexity of computer architectures, code optimisation has become the main rout...
This course covers techniques for improving the performance of parallel applications by optimising o...
This Best Practice Guide (BPG) extends the previously developed series of BPGs by providing an updat...
This Best Practice Guide provides information about Intel's Haswell/Broadwell architecture in order ...
The ARM processor is heavily used in mobile phones and has the reputation of being very energy effic...
This Best Practice Guide provides information about Intel’s Many Integrated Core (MIC) architecture ...
[[abstract]]A number recently released numerical libraries including automatically tuned linear alge...
This best practice guide provides information about Intel's MIC architecture and programming models ...
Hardware accelerators are special types of elements designed for boosting the performance of certain...
In this paper we discuss new Intel instruction extensions - Intel Advance Vector Extensions 2 (AVX2)...
Energy per Instruction (EPI) is a measure of the amount of energy expended by a microprocessor for e...
This book presents the background of the ARM architecture and outlines the features of the processor...
The authors describe an intelligent EPROM silicon compiler. The compiler accepts high-level specific...
Automated code generation and performance tuning tech-niques for concurrent architectures such as GP...
The Work Package 7 ‘Application Enabling and Support’ provides applications enabling services for HP...
In the ever-growing complexity of computer architectures, code optimisation has become the main rout...