Performance Comparison of Single-Precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core Processors

Automated code generation and performance tuning tech-niques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point com-putation in SPICE Model-Evaluation. Our Verilog AMS compiler produces code for parallel evaluation of non-linear circuit models suitable for use in SPICE simulations where the same model is evaluated several times for all the de-vices in the circuit. Our compiler uses architecture specific parallelization strategies (OpenMP for multi-core, PThreads for Cell, CUDA for GPU, statically scheduled VLIW for FPGA) when producing code for these different architec-tures. We automatically explore different implementation configurations (e.g. unroll factor, vector length) using our performance-tuner to identify the best possible configura-tion for each architecture. We demonstrate speedups of 3– 182 × for a Xilinx Virtex5 LX 330T, 1.3–33 × for an IBM Cell, and 3–131 × for an NVIDIA 9600 GT GPU over a 3GHz Intel Xeon 5160 implementation for a variety of single-precision device models