Modern Intel processors use an undisclosed hash function to map memory lines into last-level cache slices. In this work we develop a technique for reverse-engineering the hash function. We apply the technique to a 6-core Intel processor and demonstrate that knowledge of this hash function can facilitate cache-based side channel attacks, reducing the amount of work required for profiling the cache by three orders of magnitude. We also show how using the hash function we can double the number of colours used for page-colouring techniques
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
Abstract. Modern Intel processors use an undisclosed hash function to map memory lines into last-lev...
Abstract. Cache attacks, which exploit differences in timing to perform covert or side channels, are...
Dividing last level caches into slices is a popular method to prevent memory accesses from becoming ...
Abstract. Dividing last level caches into slices is a popular method to prevent memory accesses from...
Modern CPUs use a variety of undocumented microarchitectural hash functions to efficiently distribut...
In modern computing environments, hardware resources are commonly shared, and parallel computation i...
Sharing memory pages between non-trusting processes is a common method of reducing the memory footpr...
Security and trustworthiness are key considerations in designing modern processor hardware. It has b...
We expand on the idea, proposed by Kelsey et al. [14], of cache memory being used as a side-channel ...
The report describes the development of several software side-channel attacks which exploit cache v...
We present an effective implementation of the PRIME+PROBE side-channel attack against the lastlevel ...
For a distributed last level cache (LLC) in a large multicore chip, the access time to one LLC bank ...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
Abstract. Modern Intel processors use an undisclosed hash function to map memory lines into last-lev...
Abstract. Cache attacks, which exploit differences in timing to perform covert or side channels, are...
Dividing last level caches into slices is a popular method to prevent memory accesses from becoming ...
Abstract. Dividing last level caches into slices is a popular method to prevent memory accesses from...
Modern CPUs use a variety of undocumented microarchitectural hash functions to efficiently distribut...
In modern computing environments, hardware resources are commonly shared, and parallel computation i...
Sharing memory pages between non-trusting processes is a common method of reducing the memory footpr...
Security and trustworthiness are key considerations in designing modern processor hardware. It has b...
We expand on the idea, proposed by Kelsey et al. [14], of cache memory being used as a side-channel ...
The report describes the development of several software side-channel attacks which exploit cache v...
We present an effective implementation of the PRIME+PROBE side-channel attack against the lastlevel ...
For a distributed last level cache (LLC) in a large multicore chip, the access time to one LLC bank ...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...