Efficient implementation for RISC-V of the Post-Quantum Cryptography suite CRYSTALS with hardware acceleration on FPGA

The objective of this thesis is to design and implement a hardware accelerator for the CRYSTALS post-quantum cryptography suite, which consists of the public key encryption algorithm Kyber and the digital signature algorithm Dilithium. They were recently chosen by NIST as finalist for the Post-Quantum public key cryptography standard. Both Kyber and Dilithium are lattice-based cryptographic algorithms that are founded on difficult-to-solve mathematical problems in lattice structures for both classical and quantum computers. The reference code from NIST has been ported from x86 to RISC-V because the project is intended for embedded devices that use the RISC-V open architecture. Using the insight from the profiling data and the analysis of the algorithms, it has been decided to enhance the performance of the algorithms' polynomial computation sections and design an accelerator for operations between polynomials to contain resource usage. The accelerator has been developed in SystemVerilog, tested in simulation using test vectors derived from the original code, and implemented on an FPGA platform. Two different hardware platforms have been implemented on FPGA: a microcontroller-based SoC with a 32-bit RISC-V and a general-purpose SoC with a RISC-V CVA6 processor. The C software code has been heavily modified in order to fully exploit the characteristics of the hardware accelerator. An intensive benchmark campaign reports a speed-up of up to 46 times for Kyber and 21 times for Dilithium in the execution of the polynomial computation