Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture emulation of unmodified binaries. However, DBT systems face correctness and performance challenges, when emulating concurrent binaries from strong to weak memory consistency architectures. As a matter of fact, we report several translation errors in QEMU, when emulating x86 binaries on Arm hosts. To address these challenges, we propose an end-to-end approach that provides correct and efficient emulation for weak memory model architectures. Our contributions are twofold: we formalize QEMU's intermediate representation's memory model, and use it to propose formally verified mapping schemes to bridge the strong-on-weak memory consistency mismatch. Secondly, w...
International audienceFloating-point hardware support has more or less been settled 35 years ago by ...
Dynamic Binary Translators and Optimizers (DBTOs) have been established as a common architecture dur...
As hardware parallelism continues to increase, CPU caches can no longer be considered a transparent,...
Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture emulation of u...
Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture emulation of u...
Artifact for the Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures paper publ...
Abstract—Dynamic binary translation (DBT) is a core technology to many important applications such a...
International audienceDuring dynamic binary translation (DBT), guest memory accesses need to be tran...
Dynamic binary translation (DBT) is a core technology to many important applications such as system ...
Dynamic Binary Translation (DBT) requires the implementation of load-link/store-conditional (LL/SC) ...
Funding: This work was supported by a UK RISE Grant.The emergence of new architectures create a recu...
Dynamic binary translation (DBT) is a powerful tech-nique with several important applications. Syste...
System-level Dynamic Binary Translation (DBT) provides the capability to boot an Operating System (O...
Recently, reconfigurable architectures, which outperform DSP processors, have become important. Alth...
AbstractDynamic binary translation is the process of translating, modifying and rewriting executable...
International audienceFloating-point hardware support has more or less been settled 35 years ago by ...
Dynamic Binary Translators and Optimizers (DBTOs) have been established as a common architecture dur...
As hardware parallelism continues to increase, CPU caches can no longer be considered a transparent,...
Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture emulation of u...
Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture emulation of u...
Artifact for the Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures paper publ...
Abstract—Dynamic binary translation (DBT) is a core technology to many important applications such a...
International audienceDuring dynamic binary translation (DBT), guest memory accesses need to be tran...
Dynamic binary translation (DBT) is a core technology to many important applications such as system ...
Dynamic Binary Translation (DBT) requires the implementation of load-link/store-conditional (LL/SC) ...
Funding: This work was supported by a UK RISE Grant.The emergence of new architectures create a recu...
Dynamic binary translation (DBT) is a powerful tech-nique with several important applications. Syste...
System-level Dynamic Binary Translation (DBT) provides the capability to boot an Operating System (O...
Recently, reconfigurable architectures, which outperform DSP processors, have become important. Alth...
AbstractDynamic binary translation is the process of translating, modifying and rewriting executable...
International audienceFloating-point hardware support has more or less been settled 35 years ago by ...
Dynamic Binary Translators and Optimizers (DBTOs) have been established as a common architecture dur...
As hardware parallelism continues to increase, CPU caches can no longer be considered a transparent,...