Generally, image processing algorithms are suitable for parallel execution. However, this has not yet been exploited in a feasible design. Instead of the common practice, where the pixels on the sensor and the processor arrays are mapped onto each other, we propose the idea to split the image into multiple blocks of pixels (of the same size) and map each of these blocks onto one processing element. This decreases the hardware consumption and the communication overhead between the processing elements. This paper describes the architecture of the processor (the block-based image processor, BLIP) and the feasibility of low-, mid- and high-level image processing algorithms on the proposed architecture
The utilization of multiple DSP systems for parallel processing in computationally demanding applica...
The authors present a parallel algorithm for fast rendering. A set of zones which can be concurrentl...
FPGA devices in Reconfigurable Computers (RCs) al-low datapath, memory, and processing elements (PEs...
Generally, image processing algorithms are suitable for parallel execution. However, this has not ye...
Click on the DOI link to access the article (may not be free).Traditional methods for processing lar...
This paper presents a novel vision chip architecture based on pixel-neighborhood-level parallel proc...
A new processor is proposed, capable to expand the dynamic range of input images in real-time. With ...
Different tasks in image processing exhibit different computational requirements that should be cons...
Image processing in industrial vision systems requires both real-time speed and robustness. Modern c...
We consider the design process of VLSI systems dedicated to the real-time implementation of cooperat...
We develop efficient algorithms for low and intermediate level image processing on the scan line arr...
Image feature extraction is instrumental for most of the best-performing algorithms in computer vis...
A high speed Analog VLSI Image acquisition and pre-processing system is described in this paper. A 6...
ISBN: 0780373049A joint algorithm-architecture analysis leads to a new version of picture segmentati...
Real time image processing is a challenging task in which fetching the sub image requires offset mem...
The utilization of multiple DSP systems for parallel processing in computationally demanding applica...
The authors present a parallel algorithm for fast rendering. A set of zones which can be concurrentl...
FPGA devices in Reconfigurable Computers (RCs) al-low datapath, memory, and processing elements (PEs...
Generally, image processing algorithms are suitable for parallel execution. However, this has not ye...
Click on the DOI link to access the article (may not be free).Traditional methods for processing lar...
This paper presents a novel vision chip architecture based on pixel-neighborhood-level parallel proc...
A new processor is proposed, capable to expand the dynamic range of input images in real-time. With ...
Different tasks in image processing exhibit different computational requirements that should be cons...
Image processing in industrial vision systems requires both real-time speed and robustness. Modern c...
We consider the design process of VLSI systems dedicated to the real-time implementation of cooperat...
We develop efficient algorithms for low and intermediate level image processing on the scan line arr...
Image feature extraction is instrumental for most of the best-performing algorithms in computer vis...
A high speed Analog VLSI Image acquisition and pre-processing system is described in this paper. A 6...
ISBN: 0780373049A joint algorithm-architecture analysis leads to a new version of picture segmentati...
Real time image processing is a challenging task in which fetching the sub image requires offset mem...
The utilization of multiple DSP systems for parallel processing in computationally demanding applica...
The authors present a parallel algorithm for fast rendering. A set of zones which can be concurrentl...
FPGA devices in Reconfigurable Computers (RCs) al-low datapath, memory, and processing elements (PEs...