High Throughput Parallel Implementation of Blowfish Algorithm

Each day, millions of users generate and interchange large volumes of information in various fields. Cryptography plays an important role in preserving the confidentiality of data transmitted over public networks especially with rapidly growth in communication techniques. In the recent years, there is an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this article, we present high throughput efficient hardware architecture of Blowfish cryptographic algorithm.We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. In addition, the S-box tables of each round of the algorithm have been implemented in block RAMs to allow parallel data encryption. The implementation has been successfully done by virtex-5 (xc5vlx220t) FPGA device using Xilinx ISE 14.7. Our proposed architecture is very fast, it achieves a throughput of 12 Gbps and occupied 1280 slices, whereas the highest reported throughput in the literature as our knowledge is 6.3 Gbps