Efficient FPGA Implementations of Block Ciphers KHAZAD

Abstract. The technical analysis used in determining which of the NESSIE candidates will be selected as a standard block cipher includes efficiency testing of both hardware and soft-ware implementations of candidate algorithms. Reprogrammable devices such as Field Pro-grammable Gate Arrays (FPGA’s) are highly attractive options for hardware implementations of encryption algorithms and this report investigates the significance of FPGA implementa-tions of the block ciphers KHAZAD and MISTY1. A strong focus is placed on high throughput circuits and we propose designs that unroll the cipher rounds and pipeline them in order to optimize the frequency and throughput results. In addition, we implemented solutions that allow to change the plaintext and the key on a cycle-by-cycle basis with no dead cycle. The resulting designs fit on a VIRTEX1000 FPGA and have throughput between 8 and 9 Gbits/s. This is an impressive result compared with existing FPGA implementations of block ciphers within similar devices.