An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints

Multi-processor system on-chip (MPSoC) architectures represent an emerging paradigm for developing customized, application specific solutions meeting time-to-market, performance and power consumption constraints. Application-specific MPSoCs are usually designed by using a platform-based approach, where a wide range of customizable parameters must be tuned to find the best trade-offs in terms of the selected figures of merit (such as energy, delay and area). This optimization phase is called design space exploration (DSE) and it generally consists of a multi-objective optimization (MOO) problem with multiple constraints. The design space for an application-specific MPSoC architecture consists of several parameters, mainly related to micro-architecture, memory hierarchy, and interconnection network. The total amount of possible architecture configurations is too large to be comprehensively evaluated. So far, several heuristic techniques have been proposed to address the DSE problem for MPSoC, but they are not efficient in handling constraints and identifying the Pareto front. In this paper, an efficient DSE methodology for application-specific MPSoC is proposed. The methodology combines design of experiments (DoEs) and response surface modeling (RSM) techniques to a new technique for handling system-level constraints. First, the DoE phase generates an initial plan of experiments used to create a coarse view of the target design space. Then, a set of RSM techniques are used to refine the exploration by exploiting application-specific constraints to identify the maximum number of feasible solutions. To trade-off accuracy and efficiency of the proposed techniques, a set of experimental results with actual workloads are reported in the paper