A countermeasure against differential power analysis based on random delay insertion

Differential power analysis is widely recognized as an extremely powerful and low-cost technique to extract secret information from cryptographic devices. As a consequence, DPA-countermeasures have been proposed in the technical literature ranging over every abstraction level in an embedded system, from software to transistor-level techniques. In this paper, a novel gate-level countermeasure is proposed which, exploiting the insertion of random delays in the datapath of a cryptographic processor, allows to randomize not just the instantaneous current consumption profile but also the total charge quantity transferred from the power supply during a clock cycle