Evaluation of dynamic voltage and frequency scaling as a differential power analysis countermeasure

Differential power analysis (DPA) attack is a major concern for secure embedded devices (Ravi et al., 2004)-(Ors et al., 2004). Currently proposed countermeasures (Pramstaller, 2005)-(Tin and Verbauwhede, 2004) to prevent DPA imposes significant area, power and performance overheads. In addition they either require special standard cell library and design flows or algorithmic modifications. Recently, random dynamic voltage and frequency scaling (RDVFS) has been proposed (Yang et al., 2005) as a DPA countermeasure, which has less area, power and performance overheads and it does not require special cell library nor design flows nor algorithmic modifications. However, in a synchronous digital circuit, the operating frequency can be detected by monitoring glitches on the power line. In this paper, the authors show that using this information, it is possible to mount a DPA attack on circuits employing RDVFS countermeasure. The authors propose an alternative technique which only varies the supply voltage randomly. Experimental results on AES core with SPICE level simulations show that our proposed method significantly weakens the DPA attack by reducing the correlation of power to processed data