Add to ORKGIn this paper, we present a novel technique for early prediction of timing violations in high-performance pipelined microprocessors. We show that a static instruction in a microprocessor, identified by its Program Counter (PC), is an excellent predictor of an upcoming timing violation. Our analysis combines architectural data collected from real program execution with gate level logic analysis. Exploiting this PC based timing violation predictability, we propose a robust system design that predicts and tolerates timing violations seamlessly in a pipelined microprocessor. Under two different faulty environments, we show 20.9-89.8% and 14.6-80.6% average performance improvements in real programs over other state-of-the-art techniques, respect...
Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as ...
Modern processors remove many artificial constraints on instruction ordering,permitting multiple ins...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the perfo...
Timing guardbands act as a barrier protecting conventional processors from circuit-level phenomena l...
International audienceEstimating safe upper bounds on task execution times is required in the design...
Static timing analysis provides the basis for setting the clock period of a microprocessor core, bas...
In this paper, we demonstrate that the sensitized path delays in various microprocessor pipe stages ...
Previous timing analysis methods have assumed that the worst-case instruction execution time necessa...
When constructing real-time systems, safe and tight estimations of the worst case execution time (WC...
Critical real-time embedded systems feature complex safety-related, performance-demanding functional...
Static Timing Analysis is the state-of-the-art practice to ascertain the timing behaviour of current...
Abstract — Hard real-time systems need methods to deter-mine upper bounds for their execution times,...
Microelectronic scaling has entered into the nanoscale era with tremendous capacity and performance ...
Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as ...
Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as ...
Modern processors remove many artificial constraints on instruction ordering,permitting multiple ins...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the perfo...
Timing guardbands act as a barrier protecting conventional processors from circuit-level phenomena l...
International audienceEstimating safe upper bounds on task execution times is required in the design...
Static timing analysis provides the basis for setting the clock period of a microprocessor core, bas...
In this paper, we demonstrate that the sensitized path delays in various microprocessor pipe stages ...
Previous timing analysis methods have assumed that the worst-case instruction execution time necessa...
When constructing real-time systems, safe and tight estimations of the worst case execution time (WC...
Critical real-time embedded systems feature complex safety-related, performance-demanding functional...
Static Timing Analysis is the state-of-the-art practice to ascertain the timing behaviour of current...
Abstract — Hard real-time systems need methods to deter-mine upper bounds for their execution times,...
Microelectronic scaling has entered into the nanoscale era with tremendous capacity and performance ...
Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as ...
Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as ...
Modern processors remove many artificial constraints on instruction ordering,permitting multiple ins...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...