Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as an important threat to the reliability of synchronous digital circuits. To protect circuits from these timing errors, designers typically use a conservative timing margin, which leads to operational inefficiency. Existing adaptive approaches reduce such conservative margins by predicting the timing errors in advance and adjusting the timing margin adaptively. However, these error prediction approaches overlook the impact of input workload (i.e., operands) on path sensitization, thereby resulting in a loss of accuracy. The diversity of input operands leads to complex path sensitization behaviors, making them hard to represent in timing error m...
Critical real-time embedded systems feature complex safety-related, performance-demanding functional...
ISBN: 0818654104High level functional information, available in a circuit specification, can be used...
Abstract — Deeply scaled CMOS circuits are increasingly sus-ceptible to transient faults and soft er...
Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as ...
Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as ...
Circuit designers typically combat variations in hardware and workload by increasing conservative gu...
Microelectronic scaling has entered into the nanoscale era with tremendous capacity and performance ...
In this paper, we present a novel technique for early prediction of timing violations in high-perfor...
Various error models are being used in simulation of voltage-scaled arithmetic units to examine appl...
Timing analysis is a cornerstone of the digital design process. Statistical Static Timing Analysis w...
Near-threshold computing is essential for energy-efficient operation of VLSI systems, but wide perfo...
Timing guardbands act as a barrier protecting conventional processors from circuit-level phenomena l...
Abstract—In advanced technology nodes, incremental delay due to coupling is a serious concern. Desig...
This paper proposes a novel approach to modeling of gate level timing errors during high-level instr...
Nearly every synchronous digital circuit today is de-signed with timing margins. These timing margin...
Critical real-time embedded systems feature complex safety-related, performance-demanding functional...
ISBN: 0818654104High level functional information, available in a circuit specification, can be used...
Abstract — Deeply scaled CMOS circuits are increasingly sus-ceptible to transient faults and soft er...
Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as ...
Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as ...
Circuit designers typically combat variations in hardware and workload by increasing conservative gu...
Microelectronic scaling has entered into the nanoscale era with tremendous capacity and performance ...
In this paper, we present a novel technique for early prediction of timing violations in high-perfor...
Various error models are being used in simulation of voltage-scaled arithmetic units to examine appl...
Timing analysis is a cornerstone of the digital design process. Statistical Static Timing Analysis w...
Near-threshold computing is essential for energy-efficient operation of VLSI systems, but wide perfo...
Timing guardbands act as a barrier protecting conventional processors from circuit-level phenomena l...
Abstract—In advanced technology nodes, incremental delay due to coupling is a serious concern. Desig...
This paper proposes a novel approach to modeling of gate level timing errors during high-level instr...
Nearly every synchronous digital circuit today is de-signed with timing margins. These timing margin...
Critical real-time embedded systems feature complex safety-related, performance-demanding functional...
ISBN: 0818654104High level functional information, available in a circuit specification, can be used...
Abstract — Deeply scaled CMOS circuits are increasingly sus-ceptible to transient faults and soft er...