FPGA Implementation of 32-bit RISC-V Processor with Web-Based Assembler-Disassembler

In this study, a pure structural implementation based, 32-bit open source RISC-V processor is presented. The proposed processor is designed using Verilog and it is implemented on Cyclone IV 4CE115 FPGA device available on Altera DE2-115 Board. Additionally, web-based assembler and disassembler tools are developed and published as a part of this project. Before using the target RISC-V processor, the user can generate machine code using the web-based assembler tool. Then, the generated machine code can be downloaded onto the RISC-V processor using UART. The web-based assembler and disassembler tools are developed with technologies such as HTMLS, CSS and JavaScript. The proposed processor is a fully functional processor that uses RV32I base integer instructional set with 37 instructions. The amount of hardware resources used by the whole processor circuit is about 43.7% of the Cyclone IV 4CE115 FPGA device and the maximum frequency achieved for the processor is 150MHz without using any timing constraint