Fully compatible CMOS technology polysilicon nanowires for integrated gas sensing applications

Polysilicon nanowires are synthesized using a low cost classical top-down fabrication technique commonly used in microelectronic industry: the sidewall spacer formation technique. Polysilicon layer is deposited by Low Pressure Chemical Vapour Deposition technique on SiO2 wall patterned by conventional UV lithography technique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of nanometric size sidewall spacers with 50nm and 100nm curvature radius used as polysilicon nanowires]. N- and P-type in-situ doping control of these polysilicon nanowires over a large range, from 2.1016 at.cm-3 to 2.1020 at.cm-3, is demonstrated. These nanowires are integrated into the fabrication of electrical devices (resistors, transistors) and electrical properties are studied in function of in-situ doping levels. I(T) measurements show that polysilicon nanowires dark conductivity is thermally activated following the Mott or Seto's theories related to the nanowires size dependent structural quality. Charged gas species (ammonia) sensitivity of these nanowires has also been studied. In addition, feasibility of N- and P-channel polysilicon nanowires transistors is demonstrated. Such results show the full compatibility of the nanospacer polysilicon nanowires technology with the existing silicon CMOS technology using nanowires as potential sensitive units for integrated gas sensors applications