Underneath the FPGA Clothes: Enhancing Security: FPL TUTORIAL

International audienceFPGAs are primarily digital devices and application designers have to follow the usual design methodologies of digital systems when they target FPGAs. Nevertheless, when the applications include cryptographic primitives these methodologies are not sufficient to achieve the security requirements of certification. The variability of parameters of the devices, due to electronic noises, aging, environmental fluctuations and CMOS/FLASH process variations, conduce to change the design methodologies and the designers have to consider analog phenomena during the design of the digital system. At the same time, the continuous increase in the number of research projects on hardware implementation of ciphers, true random number generators (TRNG) and physical unclonable functions (PUF) highlights their scientific and practical interest. But design, evaluation and test of such cryptographic primitives are arduous especially in FPGA when the designer doesn’t control all the design parameters and the estimation of entropy sources is tricky. This half-day tutorial will provide firstly an introduction to the physical phenomena for the security of digital integrated circuit including an introduction to the randomness generation (TRNG), to the device fingerprint (PUF) generation and to the protection of cryptographic primitives against physical attacks.Random numbers are crucial in cryptography: they are used as confidential keys, initialization vectors, nonces in challenge-response protocols, padding values, hardware identifiers, and as masks in side channel attack countermeasures. Random number generators (RNGs) and physical unclonable functions (PUF) must generate random numbers that have good statistical properties and the generated sequences must be impossible to predict and manipulate. To help FPGA designers with the TRNG/PUF design and evaluation, we will discuss the design, statistical evaluation and tests of TRNGs and PUFs when implemented in FPGA