Proceedings of Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

The Thick Control Flow (TCF) model packs together selfsimilarcomputations to simplify parallel programming and to eliminateredundant usage of associated software and hardware resources.While there are processor architectures supporting native executionof programs written for the model, none of them support concurrentmemory access that can speed up execution of many algorithms by alogarithmic factor. In this paper, we propose an architectural solutionimplementing concurrent memory access for TCF-aware processors.The solution is based on bounded size step caches and two-phasestructure of the TCF-aware processors. Step caches capture and holdthe references made during the on-going step of an execution thatare independent by the definition of TCF execution and thereforeavoid coherence problems. The 2-phase structure reduces some concurrentaccesses to a frontend operation followed by broadcast in thespreading network. According to our evaluation, a concurrent memoryaccess-aware B-backend unit TCF processor executes certain algorithmsup to B times faster than the baseline TCF processor.