ISBN: 0818669055The digit-recurrence division relies on a sequence of addition/subtraction and shift operations in a manner similar to the paper-and-pencil approach, that gives a very regular structure suitable for efficient VLSI implementation. Speed is obtained through the use of redundant number notation allowing carry-propagation-free addition/subtraction with a delay independent of the size of the divisor. Since the quotient digits are obtained sequentially, the delay can theoretically be further reduced by recurring to higher-order radixes to obtain several quotient bits at once. This paper compares the synthesis of radix-2 and radix-4 dividers
The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of...
High-radix division, developing several quotient bits per clock, is usually limited by the difficult...
[[abstract]]A new floating-point division architecture that complies with the IEEE 754-1985 standard...
: The digit-recurrence division relies on a sequence of addition/subtraction and shift operations i...
The speed of SRT-type dividers is mainly determined by the complexity of the quotient-digit selectio...
This paper presents a derivation of four radix-2 division algorithms by digit recurrence. Each divis...
In this paper, we propose a class of division algorithms with the aim of reducing the delay of the s...
A new implementation for minimally redundant radix-4 SRT division with the recurrence in the signed-...
A new implementation for minimally redundant radix-4 SRT division with the recurrence in the signed-...
The speed of high-radix digit-recurrence dividers and square-root units is mainly determined by the ...
The speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the qu...
We describe a hardware-oriented design of a complex division algorithm proposed in.1 This algorithm ...
This paper presents the design of a radix-4, 32-bit integer divider which uses a recursive, non-rest...
Almost all recent microprocessors and DSP chips perform addition, subtraction, multiplication and di...
We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obta...
The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of...
High-radix division, developing several quotient bits per clock, is usually limited by the difficult...
[[abstract]]A new floating-point division architecture that complies with the IEEE 754-1985 standard...
: The digit-recurrence division relies on a sequence of addition/subtraction and shift operations i...
The speed of SRT-type dividers is mainly determined by the complexity of the quotient-digit selectio...
This paper presents a derivation of four radix-2 division algorithms by digit recurrence. Each divis...
In this paper, we propose a class of division algorithms with the aim of reducing the delay of the s...
A new implementation for minimally redundant radix-4 SRT division with the recurrence in the signed-...
A new implementation for minimally redundant radix-4 SRT division with the recurrence in the signed-...
The speed of high-radix digit-recurrence dividers and square-root units is mainly determined by the ...
The speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the qu...
We describe a hardware-oriented design of a complex division algorithm proposed in.1 This algorithm ...
This paper presents the design of a radix-4, 32-bit integer divider which uses a recursive, non-rest...
Almost all recent microprocessors and DSP chips perform addition, subtraction, multiplication and di...
We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obta...
The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of...
High-radix division, developing several quotient bits per clock, is usually limited by the difficult...
[[abstract]]A new floating-point division architecture that complies with the IEEE 754-1985 standard...