Analysis and design of nano-scale VLSI circuits considering the spatial and temporal reliability degradation

As CMOS scaling moves towards the end of technology road map, a plethora of reliability issues are emerging as challenging obstacles for designing a stable/robust circuit system. Reliability issues in nano-scale designs can be broadly categorized into spatial and temporal components. Spatial reliability of nano-scale circuits are mainly endangered by the variation in various process parameters, while temporal reliability issue stems from a number of time-dependent degradation mechanisms such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). In this thesis, various circuit analysis and design techniques considering these reliability problems are presented. In the second chapter, a statistical static timing analysis (SSTA) algorithm is proposed to accurately estimate the distribution of maximum delay of given design under process variation. Next, in the third chapter, an on-chip variability sensor using phase locked loop (PLL) is proposed. The proposed PLL based sensor can accurately capture various sources of circuit variability, and can be used to generate an optimal body bias signal to prevent target ICs from any possible timing failures. The later four chapters introduce the temporal reliability issues related to NBTI. In the fourth and fifth chapters, the impact of temporal NBTI degradation in random logic circuit and SRAM memory array is addressed and modeled in compact analytical forms. Using the proposed NBTI model, a realistic reliability characterization method based on a post-silicon IDDQ measurement is presented. It will be shown that IDDQ decrease under NBTI reveals a specific trend which can be used to identify and predict temporal performance degradation in target IC. Finally, in chapter seven, a more generalized NBTI model considering the stochastic distribution of interfacial traps is introduced. Based on the model, we will show that NBTI in short channel device can experience a random variation during its degradation, and can severely impact circuit reliability in scaled technologies