Reliability analysis of dynamic logic circuits under transistor aging effects in nanotechnology

As the CMOS technology scales down towards nanoscale dimensions, there are increasing transistor reliability challenges which impact the lifetime of integrated circuits. These issues are known as aging effects, which result in degradation of the performance of circuits. NBTI (Negative biased temperature instability) is a well known aging phenomenon which is also one of the limiting factors for future scaling of devices. In this project we will analyze the impact of NBTI on performance of dynamic logic circuits. Dynamic logic is a popular design methodology in high speed digital electronics. We will first analyze the impact of NBTI on performance metrics of a dynamic logic circuit, namely, delay, power, and Unity Noise Gain (UNG). It is observed that the aging of the PMOS keeper transistor and the PMOS in the output inverter of a dynamic logic circuit have opposing effects of the dynamic logic circuit performance under NBTI. This provides the opportunity to nullify the effect of NBTI on aging of a dynamic logic circuit by carefully optimizing the sizing of the keeper and the inverter PMOS transistors. We propose PMOS sizing optimization to reduce the impact of the reliability issues in dynamic logic circuits. Our results show that optimal sizing of the PMOS transistors in a dynamic logic circuit, the circuit becomes immune to the NBTI aging effect. After the optimization, the degradations in delay, power, and UNG over a 2-year lifetime are measured to be 1.71%, 0%, and 0% in a 32nm CMOS technology. In a nonoptimized circuit, this degradation is too high to be ignored