Automatic Fixed-Point Conversion: a Gateway to High-Level Power Optimization

International audienceGiven that Moore’s law scaling has hit the power-wall, reducing power consumption of high-performance embedded systems becomes very crucial. It is also well admitted that system-level techniques offer the greatest potential for optimizing power. In this tutorial, we demonstrate how the careful tuning of the fixed-point arithmetic used to implement numerous functionalities in embedded system applications, can lead to significant savings in power consumption. Interestingly, proper dimensioning of the bit widths used to represent signals or variables can reduce the power consumption in both hardware and software implementations. Even in software implementation, the pervasive use of Single Instruction Multiple Data (SIMD) datapaths in modern processors is pushing designers to meddle with bit allocation. Often, a reduction in bit widths can enable the use of more SIMD slots, which increases the parallelism boosting the speed and energy efficiency of the software implementation.Although quantization effects in digital signal processing systems have been studied since the 70’s, significant progress has been made in the recent years. This tutorial packs nearly a decade of research in designing systems with fixed-point arithmetic. We expose the deficiency in the support offered by existing EDA tools and motivate the need for new solutions. Accordingly, we put into perspective several recent techniques that have been developed to facilitate a quick analysis of the impact of a selected fixed-point format on the system performance and cost. We analyze the fixed-point refinement in a comprehensive way from a tools perspective, dividing the problem into various design steps (e.g., range and precision analysis). For each step, we present concrete solutions amenable to design automation that are illustrated with multiple relevant design examples from the wireless communication, multi-media and other signal processing domains