Stack Data Engine

This report is a description of the design and implementatlon of the GR microprocessor, an eight bit stack machine with hierarchical procedure calls. The processor is an experiment in computer implementation, and features a microcoded control section. Interface to Memory and I/O is provided in order to test operation of the machine. The total time from start to completion of this project was two and one half weeks, not including an extra week for completlon of this document. As a result of this schedule certain shortcuts were taken, particularly in the layout of the chip. The experience gained has been invaluable, though, and we hope to complete a successor to this version in the upcomlng year, The results of many of the mistakes have been summarized in section 5, where they can hopefully benefit others. This chip was designed partially as a project for CS-181 class at Caltech. The architecture and instruction set are based on earlier work done on a Pascal compiler for CS-138 class at Caltech during the winter of 1979. The GR acronym stands, of course, for Greg and Richard. We would like to thank Dave Johannson for supplying a data path to our specification via Bristle Blocks, and his general counseling on the design