Design of a multiple processor / shared memory controller for real-time applications

Includes bibliographical references (page 57)Throughout the history of Computer Science, one of\ud the main objectives in the development of new systems and\ud architectures has been to increase the systems performance.\ud Towards this goal, this thesis proposes a design for a\ud Multiple Processor I Shared Memory Controller for use in a\ud real-time environment. The Shared Memory Controller (SMC)\ud is a device that allows a number of Host computers access to\ud a shared memory in a concurrent fashion. The SMC provides\ud many built-in functions that would normally be performed in\ud the Host computers, thus offloading much of the typical\ud burdens of processing from them. The Multiple Processor\ud Shared Memory Controller is designed as a back-end\ud processor in a real-time data processing environment. The\ud performance increase over typical single processor systems\ud is due to the fact that this system is designed to process\ud far more data in a similar time frame.\ud The SMC can be programmed to suit the individual needs\ud of the user. It consists of a number of microprocessors,\ud called Processing Elements, connected together via a\ud specially designed message bus. The SMC interfaces to\ud multiple Host computers through a network, and sends\ud information back and forth, as well as internally, through\ud the use of message commands