Simulation of a pipelined datapath for a Very Long Instruction Word (VLIW) processor using Verilog

Thesis (M.S.) California State University, Los Angeles, 2012Committee members: Charles Liu, Kamaran Karimlou, Fred DaneshgaranDatapath, Pipelines, Processor, Verilog, VLIW, XILINXWhen any processor architecture is designed the main consideration is how to maximize the data throughput in a single clock cycle [1]. With the demand of high performance with low operating power, the Very Long Instruction Word (VLIW) architecture has an advantage when compared with traditional pipeline processors. The VLIW architecture has simple hardware and the ability to execute multiple instructions in one clock cycle.In a VLIW processor basic RICS or CISC operations are combined in one VLIW word instruction. Multiple RISC or CISC type operations can be executed in parallel using one VLIW word to give highest throughput. The more operations that are combined into a VLIW word, the higher the degree of instruction-level parallelism can be accomplished, yielding a higher-throughput [2]. The overall throughput can also increase with the help of pipelining technology [1]. The VLIW architecture favors fast execution by pre-compiling the program [3], and hence, reducing the load of finding dependencies by the hardware. Thus, VLIW processor requires a powerful compiler. In that way, it reduces the complexity of the hardware, which ultimately reduces the operating power and reduces the on chip die area. It also increases the speed of the processor.Based on the description above, a VLIW processor is designed in this thesis. I adopted a basic RISC instruction set for the study. All the basic operations of this instruction set have been implemented for this VLIW processor. The simulation results for every operation also verify the correctness of design. Moreover, a pipelining architecture is used to achieve higher concurrent execution. The data dependencies between stages are also taken care of by data forwarding and early execution techniques