Characterizing Security Monitor and Embedded System Performance across Distinct RISC-V IP-Cores

Embedded systems have seen a rapid integration into all forms of industry as they continue to shrink in size and cost. The increased demand has highlighted a need for secure systems that are robust to attacks and demonstrate reliable performance, especially if the system operation is time-critical. E orts to characterize the performance of secure systems have been obstructed either by proprietary restrictions or ineffective analysis. Proprietary technology limits a comprehensive validation of a system\u27s security and the implications it might have on performance. Performance analysis that is disclosed often lacks sufficient statistical rigor needed for a complex system. A non-proprietary processor standard, called RISC-V, may allow sufficient transparency to thoroughly model performance trade-offs. This research shows that a security platform and embedded system performance can be characterized through non-parametric statistics methodology, and provides a substantive foundation to scrutinize system design considerations that impact performance. This work proposes a new framework, the SPARC, that pioneers a synthesis of difference and equivalence hypothesis testing to provide relevant conclusions. SPARC is used to characterize performance of three RISC-V embedded systems with and without a security platform, Keystone, instantiated on an FPGA