With the arrival of multicore chips as the commodity architecture for a wide range of platforms, there is a growing pressure to make parallel programming the norm. Unfortunately, most current programmers find parallel programming too complex. Therefore, we need tools, models, and architectures that make multiprocessors more programmable. One compelling way to improve programmability is to enable back-and-forth time travel of multiprocessor execution. Such ability simplifies parallel code debugging, and is possible using a technique called Deterministic Replay of Execution. This thesis presents DeLorean, a novel hardware substrate for deterministic replay of multiprocessor systems. DeLorean advances the state of the art in that it ...
Today's hardware is becoming more and more parallel. While embarrassingly parallel codes, such as hi...
Over the last few years, the major chip manufactures have shifted from single core towards multicore...
While a lot of work has been focused on design and programming of shared memory multi-core architect...
With the arrival of multicore chips as the commodity architecture for a wide range of platforms, th...
With the arrival of multicore chips as the commodity architecture for a wide range of platforms, the...
While deterministic replay of parallel programs is a power-ful technique, current proposals have sho...
Current schemes for deterministic replay of parallel applica-tions can be of great help for programm...
This thesis contributes to the area of hardware support for parallel programming by introducing new ...
Record and deterministic Replay (RnR) is a primitive with many proposed applications in computer sys...
We introduce uniparallelism: a new style of execution that allows multithreaded applications to bene...
Journal ArticleA variation of the Time Warp parallel discrete event simulation mechanism is presente...
Multiprocessing systems have the potential for increasing system speed over what is now offered by d...
This thesis describes fast and deterministic deadlock avoidance methods that are easily applicable t...
With ubiquitous multi-core architectures, a major challenge is how to effectively use these machines...
Clusters of shared-memory symmetric multiprocessors are increasingly used for high performance...
Today's hardware is becoming more and more parallel. While embarrassingly parallel codes, such as hi...
Over the last few years, the major chip manufactures have shifted from single core towards multicore...
While a lot of work has been focused on design and programming of shared memory multi-core architect...
With the arrival of multicore chips as the commodity architecture for a wide range of platforms, th...
With the arrival of multicore chips as the commodity architecture for a wide range of platforms, the...
While deterministic replay of parallel programs is a power-ful technique, current proposals have sho...
Current schemes for deterministic replay of parallel applica-tions can be of great help for programm...
This thesis contributes to the area of hardware support for parallel programming by introducing new ...
Record and deterministic Replay (RnR) is a primitive with many proposed applications in computer sys...
We introduce uniparallelism: a new style of execution that allows multithreaded applications to bene...
Journal ArticleA variation of the Time Warp parallel discrete event simulation mechanism is presente...
Multiprocessing systems have the potential for increasing system speed over what is now offered by d...
This thesis describes fast and deterministic deadlock avoidance methods that are easily applicable t...
With ubiquitous multi-core architectures, a major challenge is how to effectively use these machines...
Clusters of shared-memory symmetric multiprocessors are increasingly used for high performance...
Today's hardware is becoming more and more parallel. While embarrassingly parallel codes, such as hi...
Over the last few years, the major chip manufactures have shifted from single core towards multicore...
While a lot of work has been focused on design and programming of shared memory multi-core architect...