International audienceCache compression algorithms must abide by hardware constraints; thus, their efficiency ends up being low, and most cache lines end up barely compressed. Moreover, schemes that compress relatively well often decompress slowly, and vice versa. This paper proposes a compression scheme achieving high (good) compaction ratio and fast decompression latency. The key observation is that by further subdividing the chunks of data being compressed one can tailor the algorithms. This concept is orthogonal to most existent compressors, and results in a reduction of their average compressed size. In particular, we leverage this concept to boost a single-cycle-decompression compressor to reach a compressibility level competitive to ...
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compressio...
The effective size of an L2 cache can be increased by using a dictionary-based compression scheme. N...
Caches are essential to today's microprocessors. They close the huge speed gap between processors an...
International audienceCache compression algorithms must abide by hardware constraints; thus, their e...
International audienceCache compression seeks the benefits of a larger cache with the area and power...
Hardware compression techniques are typically simplifications of software compression methods. They ...
International audienceHardware cache compression derives from software-compression research; yet, it...
With the widening gap between processor and memory speeds, memory system designers may find cache co...
On-chip caches are essential as they bridge the growing speed-gap between off-chip memory and proces...
International audienceThe effectiveness of a compressed cache depends on three features: i) th...
This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardw...
Processors face steep penalties when accessing on-chip memory in the form of high latency. On-chip c...
Virtual ConferenceInternational audienceCompressed cache layouts require adding the block's size inf...
Storing data in compressed form is becoming common practice in high-performance systems, where memor...
Abstract — Cache compression seeks the benefits of a larger cache with the area and power of a small...
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compressio...
The effective size of an L2 cache can be increased by using a dictionary-based compression scheme. N...
Caches are essential to today's microprocessors. They close the huge speed gap between processors an...
International audienceCache compression algorithms must abide by hardware constraints; thus, their e...
International audienceCache compression seeks the benefits of a larger cache with the area and power...
Hardware compression techniques are typically simplifications of software compression methods. They ...
International audienceHardware cache compression derives from software-compression research; yet, it...
With the widening gap between processor and memory speeds, memory system designers may find cache co...
On-chip caches are essential as they bridge the growing speed-gap between off-chip memory and proces...
International audienceThe effectiveness of a compressed cache depends on three features: i) th...
This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardw...
Processors face steep penalties when accessing on-chip memory in the form of high latency. On-chip c...
Virtual ConferenceInternational audienceCompressed cache layouts require adding the block's size inf...
Storing data in compressed form is becoming common practice in high-performance systems, where memor...
Abstract — Cache compression seeks the benefits of a larger cache with the area and power of a small...
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compressio...
The effective size of an L2 cache can be increased by using a dictionary-based compression scheme. N...
Caches are essential to today's microprocessors. They close the huge speed gap between processors an...